1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
|
dnl PowerPC-64 mpn_mul_basecase.
dnl Copyright 1999-2001, 2003-2006, 2008 Free Software Foundation, Inc.
dnl This file is part of the GNU MP Library.
dnl
dnl The GNU MP Library is free software; you can redistribute it and/or modify
dnl it under the terms of either:
dnl
dnl * the GNU Lesser General Public License as published by the Free
dnl Software Foundation; either version 3 of the License, or (at your
dnl option) any later version.
dnl
dnl or
dnl
dnl * the GNU General Public License as published by the Free Software
dnl Foundation; either version 2 of the License, or (at your option) any
dnl later version.
dnl
dnl or both in parallel, as here.
dnl
dnl The GNU MP Library is distributed in the hope that it will be useful, but
dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
dnl for more details.
dnl
dnl You should have received copies of the GNU General Public License and the
dnl GNU Lesser General Public License along with the GNU MP Library. If not,
dnl see https://www.gnu.org/licenses/.
include(`../config.m4')
C cycles/limb
C POWER3/PPC630 6-18
C POWER4/PPC970 8
C POWER5 8
C POWER6 24
C INPUT PARAMETERS
define(`rp', `r3')
define(`up', `r4')
define(`un', `r5')
define(`vp', `r6')
define(`vn', `r7')
define(`v0', `r25')
define(`outer_rp', `r22')
define(`outer_up', `r23')
ASM_START()
PROLOGUE(mpn_mul_basecase)
C Special code for un <= 2, for efficiency of these important cases,
C and since it simplifies the default code.
cmpdi cr0, un, 2
bgt cr0, L(un_gt2)
cmpdi cr6, vn, 1
ld r7, 0(vp)
ld r5, 0(up)
mulld r8, r5, r7 C weight 0
mulhdu r9, r5, r7 C weight 1
std r8, 0(rp)
beq cr0, L(2x)
std r9, 8(rp)
blr
ALIGN(16)
L(2x): ld r0, 8(up)
mulld r8, r0, r7 C weight 1
mulhdu r10, r0, r7 C weight 2
addc r9, r9, r8
addze r10, r10
bne cr6, L(2x2)
std r9, 8(rp)
std r10, 16(rp)
blr
ALIGN(16)
L(2x2): ld r6, 8(vp)
nop
mulld r8, r5, r6 C weight 1
mulhdu r11, r5, r6 C weight 2
addc r9, r9, r8
std r9, 8(rp)
adde r11, r11, r10
mulld r12, r0, r6 C weight 2
mulhdu r0, r0, r6 C weight 3
addze r0, r0
addc r11, r11, r12
addze r0, r0
std r11, 16(rp)
std r0, 24(rp)
blr
L(un_gt2):
std r31, -8(r1)
std r30, -16(r1)
std r29, -24(r1)
std r28, -32(r1)
std r27, -40(r1)
std r26, -48(r1)
std r25, -56(r1)
std r24, -64(r1)
std r23, -72(r1)
std r22, -80(r1)
mr outer_rp, rp
mr outer_up, up
ld v0, 0(vp) C new v limb
addi vp, vp, 8
ld r26, 0(up)
rldicl. r0, un, 0,62 C r0 = n & 3, set cr0
cmpdi cr6, r0, 2
addi un, un, 1 C compute count...
srdi un, un, 2 C ...for ctr
mtctr un C copy inner loop count into ctr
beq cr0, L(b0)
blt cr6, L(b1)
beq cr6, L(b2)
ALIGN(16)
L(b3): mulld r0, r26, v0
mulhdu r12, r26, v0
addic r0, r0, 0
std r0, 0(rp)
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_m_3)
ALIGN(16)
L(lo_m_3):
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 24(up)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r27, 32(up)
nop
adde r0, r0, r12
adde r24, r24, r31
mulld r9, r26, v0
mulhdu r10, r26, v0
ld r26, 40(up)
nop
mulld r11, r27, v0
mulhdu r12, r27, v0
ld r27, 48(up)
std r0, 8(rp)
adde r9, r9, r8
std r24, 16(rp)
adde r11, r11, r10
std r9, 24(rp)
addi up, up, 32
std r11, 32(rp)
addi rp, rp, 32
bdnz L(lo_m_3)
ALIGN(16)
L(end_m_3):
mulld r0, r26, v0
mulhdu r31, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
adde r0, r0, r12
adde r24, r24, r31
std r0, 8(rp)
std r24, 16(rp)
addze r8, r8
std r8, 24(rp)
addic. vn, vn, -1
beq L(ret)
ALIGN(16)
L(outer_lo_3):
mtctr un C copy inner loop count into ctr
addi rp, outer_rp, 8
mr up, outer_up
addi outer_rp, outer_rp, 8
ld v0, 0(vp) C new v limb
addi vp, vp, 8
ld r26, 0(up)
ld r28, 0(rp)
mulld r0, r26, v0
mulhdu r12, r26, v0
addc r0, r0, r28
std r0, 0(rp)
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_3)
ALIGN(16) C registers dying
L(lo_3):
mulld r0, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 24(up) C
ld r28, 8(rp) C
mulld r24, r27, v0 C
mulhdu r8, r27, v0 C 27
ld r27, 32(up) C
ld r29, 16(rp) C
adde r0, r0, r12 C 0 12
adde r24, r24, r10 C 24 10
mulld r9, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 40(up) C
ld r30, 24(rp) C
mulld r11, r27, v0 C
mulhdu r12, r27, v0 C 27
ld r27, 48(up) C
ld r31, 32(rp) C
adde r9, r9, r8 C 8 9
adde r11, r11, r10 C 10 11
addze r12, r12 C 12
addc r0, r0, r28 C 0 28
std r0, 8(rp) C 0
adde r24, r24, r29 C 7 29
std r24, 16(rp) C 7
adde r9, r9, r30 C 9 30
std r9, 24(rp) C 9
adde r11, r11, r31 C 11 31
std r11, 32(rp) C 11
addi up, up, 32 C
addi rp, rp, 32 C
bdnz L(lo_3) C
ALIGN(16)
L(end_3):
mulld r0, r26, v0
mulhdu r10, r26, v0
ld r28, 8(rp)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r29, 16(rp)
nop
adde r0, r0, r12
adde r24, r24, r10
addze r8, r8
addc r0, r0, r28
std r0, 8(rp)
adde r24, r24, r29
std r24, 16(rp)
addze r8, r8
std r8, 24(rp)
addic. vn, vn, -1
bne L(outer_lo_3)
b L(ret)
ALIGN(16)
L(b0): ld r27, 8(up)
addi up, up, 8
mulld r0, r26, v0
mulhdu r10, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
addc r24, r24, r10
addze r12, r8
std r0, 0(rp)
std r24, 8(rp)
addi rp, rp, 8
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_m_0)
ALIGN(16)
L(lo_m_0):
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 24(up)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r27, 32(up)
nop
adde r0, r0, r12
adde r24, r24, r31
mulld r9, r26, v0
mulhdu r10, r26, v0
ld r26, 40(up)
nop
mulld r11, r27, v0
mulhdu r12, r27, v0
ld r27, 48(up)
std r0, 8(rp)
adde r9, r9, r8
std r24, 16(rp)
adde r11, r11, r10
std r9, 24(rp)
addi up, up, 32
std r11, 32(rp)
addi rp, rp, 32
bdnz L(lo_m_0)
ALIGN(16)
L(end_m_0):
mulld r0, r26, v0
mulhdu r31, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
adde r0, r0, r12
adde r24, r24, r31
std r0, 8(rp)
addze r8, r8
std r24, 16(rp)
addic. vn, vn, -1
std r8, 24(rp)
nop
beq L(ret)
ALIGN(16)
L(outer_lo_0):
mtctr un C copy inner loop count into ctr
addi rp, outer_rp, 16
addi up, outer_up, 8
addi outer_rp, outer_rp, 8
ld v0, 0(vp) C new v limb
addi vp, vp, 8
ld r26, -8(up)
ld r27, 0(up)
ld r28, -8(rp)
ld r29, 0(rp)
nop
nop
mulld r0, r26, v0
mulhdu r10, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
addc r24, r24, r10
addze r12, r8
addc r0, r0, r28
std r0, -8(rp)
adde r24, r24, r29
std r24, 0(rp)
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_0)
ALIGN(16) C registers dying
L(lo_0):
mulld r0, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 24(up) C
ld r28, 8(rp) C
mulld r24, r27, v0 C
mulhdu r8, r27, v0 C 27
ld r27, 32(up) C
ld r29, 16(rp) C
adde r0, r0, r12 C 0 12
adde r24, r24, r10 C 24 10
mulld r9, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 40(up) C
ld r30, 24(rp) C
mulld r11, r27, v0 C
mulhdu r12, r27, v0 C 27
ld r27, 48(up) C
ld r31, 32(rp) C
adde r9, r9, r8 C 8 9
adde r11, r11, r10 C 10 11
addze r12, r12 C 12
addc r0, r0, r28 C 0 28
std r0, 8(rp) C 0
adde r24, r24, r29 C 7 29
std r24, 16(rp) C 7
adde r9, r9, r30 C 9 30
std r9, 24(rp) C 9
adde r11, r11, r31 C 11 31
std r11, 32(rp) C 11
addi up, up, 32 C
addi rp, rp, 32 C
bdnz L(lo_0) C
ALIGN(16)
L(end_0):
mulld r0, r26, v0
mulhdu r10, r26, v0
ld r28, 8(rp)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r29, 16(rp)
nop
adde r0, r0, r12
adde r24, r24, r10
addze r8, r8
addic. vn, vn, -1
addc r0, r0, r28
std r0, 8(rp)
adde r24, r24, r29
std r24, 16(rp)
addze r8, r8
std r8, 24(rp)
bne L(outer_lo_0)
b L(ret)
ALIGN(16)
L(b1): ld r27, 8(up)
nop
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 16(up)
mulld r24, r27, v0
mulhdu r8, r27, v0
mulld r9, r26, v0
mulhdu r10, r26, v0
addc r24, r24, r31
adde r9, r9, r8
addze r12, r10
std r0, 0(rp)
std r24, 8(rp)
std r9, 16(rp)
addi up, up, 16
addi rp, rp, 16
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_m_1)
ALIGN(16)
L(lo_m_1):
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 24(up)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r27, 32(up)
nop
adde r0, r0, r12
adde r24, r24, r31
mulld r9, r26, v0
mulhdu r10, r26, v0
ld r26, 40(up)
nop
mulld r11, r27, v0
mulhdu r12, r27, v0
ld r27, 48(up)
std r0, 8(rp)
adde r9, r9, r8
std r24, 16(rp)
adde r11, r11, r10
std r9, 24(rp)
addi up, up, 32
std r11, 32(rp)
addi rp, rp, 32
bdnz L(lo_m_1)
ALIGN(16)
L(end_m_1):
mulld r0, r26, v0
mulhdu r31, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
adde r0, r0, r12
adde r24, r24, r31
std r0, 8(rp)
addze r8, r8
std r24, 16(rp)
addic. vn, vn, -1
std r8, 24(rp)
nop
beq L(ret)
ALIGN(16)
L(outer_lo_1):
mtctr un C copy inner loop count into ctr
addi rp, outer_rp, 24
addi up, outer_up, 16
addi outer_rp, outer_rp, 8
ld v0, 0(vp) C new v limb
addi vp, vp, 8
ld r26, -16(up)
ld r27, -8(up)
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 0(up)
ld r28, -16(rp)
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r29, -8(rp)
ld r30, 0(rp)
mulld r9, r26, v0
mulhdu r10, r26, v0
addc r24, r24, r31
adde r9, r9, r8
addze r12, r10
addc r0, r0, r28
std r0, -16(rp)
adde r24, r24, r29
std r24, -8(rp)
adde r9, r9, r30
std r9, 0(rp)
ld r26, 8(up)
ld r27, 16(up)
bdz L(end_1)
ALIGN(16) C registers dying
L(lo_1):
mulld r0, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 24(up) C
ld r28, 8(rp) C
mulld r24, r27, v0 C
mulhdu r8, r27, v0 C 27
ld r27, 32(up) C
ld r29, 16(rp) C
adde r0, r0, r12 C 0 12
adde r24, r24, r10 C 24 10
mulld r9, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 40(up) C
ld r30, 24(rp) C
mulld r11, r27, v0 C
mulhdu r12, r27, v0 C 27
ld r27, 48(up) C
ld r31, 32(rp) C
adde r9, r9, r8 C 8 9
adde r11, r11, r10 C 10 11
addze r12, r12 C 12
addc r0, r0, r28 C 0 28
std r0, 8(rp) C 0
adde r24, r24, r29 C 7 29
std r24, 16(rp) C 7
adde r9, r9, r30 C 9 30
std r9, 24(rp) C 9
adde r11, r11, r31 C 11 31
std r11, 32(rp) C 11
addi up, up, 32 C
addi rp, rp, 32 C
bdnz L(lo_1) C
ALIGN(16)
L(end_1):
mulld r0, r26, v0
mulhdu r10, r26, v0
ld r28, 8(rp)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r29, 16(rp)
nop
adde r0, r0, r12
adde r24, r24, r10
addze r8, r8
addic. vn, vn, -1
addc r0, r0, r28
std r0, 8(rp)
adde r24, r24, r29
std r24, 16(rp)
addze r8, r8
std r8, 24(rp)
bne L(outer_lo_1)
b L(ret)
ALIGN(16)
L(b2): ld r27, 8(up)
addi up, up, -8
addi rp, rp, -8
li r12, 0
addic r12, r12, 0
ALIGN(16)
L(lo_m_2):
mulld r0, r26, v0
mulhdu r31, r26, v0
ld r26, 24(up)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r27, 32(up)
nop
adde r0, r0, r12
adde r24, r24, r31
mulld r9, r26, v0
mulhdu r10, r26, v0
ld r26, 40(up)
nop
mulld r11, r27, v0
mulhdu r12, r27, v0
ld r27, 48(up)
std r0, 8(rp)
adde r9, r9, r8
std r24, 16(rp)
adde r11, r11, r10
std r9, 24(rp)
addi up, up, 32
std r11, 32(rp)
addi rp, rp, 32
bdnz L(lo_m_2)
ALIGN(16)
L(end_m_2):
mulld r0, r26, v0
mulhdu r31, r26, v0
mulld r24, r27, v0
mulhdu r8, r27, v0
adde r0, r0, r12
adde r24, r24, r31
std r0, 8(rp)
addze r8, r8
std r24, 16(rp)
addic. vn, vn, -1
std r8, 24(rp)
nop
beq L(ret)
ALIGN(16)
L(outer_lo_2):
mtctr un C copy inner loop count into ctr
addi rp, outer_rp, 0
addi up, outer_up, -8
addi outer_rp, outer_rp, 8
ld v0, 0(vp) C new v limb
addi vp, vp, 8
ld r26, 8(up)
ld r27, 16(up)
li r12, 0
addic r12, r12, 0
ALIGN(16) C registers dying
L(lo_2):
mulld r0, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 24(up) C
ld r28, 8(rp) C
mulld r24, r27, v0 C
mulhdu r8, r27, v0 C 27
ld r27, 32(up) C
ld r29, 16(rp) C
adde r0, r0, r12 C 0 12
adde r24, r24, r10 C 24 10
mulld r9, r26, v0 C
mulhdu r10, r26, v0 C 26
ld r26, 40(up) C
ld r30, 24(rp) C
mulld r11, r27, v0 C
mulhdu r12, r27, v0 C 27
ld r27, 48(up) C
ld r31, 32(rp) C
adde r9, r9, r8 C 8 9
adde r11, r11, r10 C 10 11
addze r12, r12 C 12
addc r0, r0, r28 C 0 28
std r0, 8(rp) C 0
adde r24, r24, r29 C 7 29
std r24, 16(rp) C 7
adde r9, r9, r30 C 9 30
std r9, 24(rp) C 9
adde r11, r11, r31 C 11 31
std r11, 32(rp) C 11
addi up, up, 32 C
addi rp, rp, 32 C
bdnz L(lo_2) C
ALIGN(16)
L(end_2):
mulld r0, r26, v0
mulhdu r10, r26, v0
ld r28, 8(rp)
nop
mulld r24, r27, v0
mulhdu r8, r27, v0
ld r29, 16(rp)
nop
adde r0, r0, r12
adde r24, r24, r10
addze r8, r8
addic. vn, vn, -1
addc r0, r0, r28
std r0, 8(rp)
adde r24, r24, r29
std r24, 16(rp)
addze r8, r8
std r8, 24(rp)
bne L(outer_lo_2)
b L(ret)
L(ret): ld r31, -8(r1)
ld r30, -16(r1)
ld r29, -24(r1)
ld r28, -32(r1)
ld r27, -40(r1)
ld r26, -48(r1)
ld r25, -56(r1)
ld r24, -64(r1)
ld r23, -72(r1)
ld r22, -80(r1)
blr
EPILOGUE()
|
