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| author | Thomas Voss <mail@thomasvoss.com> | 2024-06-21 23:36:36 +0200 |
|---|---|---|
| committer | Thomas Voss <mail@thomasvoss.com> | 2024-06-21 23:42:26 +0200 |
| commit | a89a14ef5da44684a16b204e7a70460cc8c4922a (patch) | |
| tree | b23b4c6b155977909ef508fdae2f48d33d802813 /vendor/gmp-6.3.0/mpn/x86_64/fastsse/README | |
| parent | 1db63fcedab0b288820d66e100b1877b1a5a8851 (diff) | |
Basic constant folding implementation
Diffstat (limited to 'vendor/gmp-6.3.0/mpn/x86_64/fastsse/README')
| -rw-r--r-- | vendor/gmp-6.3.0/mpn/x86_64/fastsse/README | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/vendor/gmp-6.3.0/mpn/x86_64/fastsse/README b/vendor/gmp-6.3.0/mpn/x86_64/fastsse/README new file mode 100644 index 0000000..5538b2d --- /dev/null +++ b/vendor/gmp-6.3.0/mpn/x86_64/fastsse/README @@ -0,0 +1,22 @@ +This directory contains code for x86-64 processors with fast +implementations of SSE operations, hence the name "fastsse". + +Current processors that might benefit from this code are: + + AMD K10 + AMD Bulldozer/Piledriver/Steamroller/Excavator + Intel Nocona + Intel Nehalem/Westmere + Intel Sandybridge/Ivybridge + Intel Haswell/Broadwell + VIA Nano + +Current processors that do not benefit from this code are: + + AMD K8 + AMD Bobcat + Intel Atom + +Intel Conroe/Penryn is a border case; its handling of non-aligned +128-bit memory operands is poor. VIA Nano also have poor handling of +non-aligned operands. |